How to track the lost mobile?

Each mobile carries a unique IMEI i.e. International Mobile Identity No

Which can be used to track your mobile anywhere in the world?

This is how it works!!!!!!

1. Dial *#06# from your mobile.

2. Your mobile shows a unique 15 digit.

3.Note down this no anywhere but except your mobile as this is the no which will help trace your mobile in case of a theft.

4. Once stolen you just have to mail this 15 digit IMEI no. tocop@vsnl.net

5. No need to go to police.

6. Your Mobile will be traced within next 24 hrs via a complex system of GPRS and internet.

7. You will find where your hand set is being operated even in case your no is being changed.

Engineering VHDL LAB programs

1. PROGRAM FOR REALIZATION OF GATES

LIBRARY IEEE;
USE IEEE..STD_LOGIC_1164.ALL;
USE IEEE..STD_LOGIC_ARITH.ALL;
USE IEEE..STD_LOGIC_UNSIGNED.ALL;

ENTITY GATES IS
PORT ( AIN : IN STD_LOGIC;
BIN : IN STD_LOGIC;
OP_NOT : OUT STD_LOGIC;
OP_OR : OUT STD_LOGIC;
OP_AND : OUT STD_LOGIC;
OP_NOR : OUT STD_LOGIC;
OP_NAND : OUT STD_LOGIC;
OP_XOR : OUT STD_LOGIC;
OP_XNOR : OUT STD_LOGIC);
END GATES;



ARCHITECTURE BEHAVIORAL OF GATES IS
BEGIN
OP_NOT <= NOT AIN;
OP_OR <= AIN OR BIN;
OP_AND <= AIN AND BIN;
OP_NOR <= AIN NOR BIN;
OP_NAND <= AIN NAND BIN;
OP_XOR <= AIN XOR BIN;
OP_XNOR <= AIN XNOR BIN;
END BEHAVIORAL;









2. PROGRAM FOR 2:4 DECODERS

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Decoder is
Port ( En : in STD_LOGIC;
D_in : in STD_LOGIC_VECTOR (1 downto 0);
D_out : out STD_LOGIC_VECTOR (3 downto 0));
end Decoder;

architecture Behavioral of Decoder is
begin
PROCESS (En,D_IN)
BEGIN
IF (En = '1') THEN
D_OUT <= "0000";
ELSE
CASE D_IN IS
WHEN "00" => D_OUT <= "0001";
WHEN "01" => D_OUT <= "0010";
WHEN "10" => D_OUT <= "0100";
WHEN "11" => D_OUT <= "1000";
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS;


end Behavioral;
Result:










3. PROGRAM FOR 8:3 ENCODERS (WITHOUT PRIORITY)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity encoder is
Port ( Enable : in STD_LOGIC;
D_in : in STD_LOGIC_VECTOR (7 downto 0);
D_out : out STD_LOGIC_VECTOR (2 downto 0));
end encoder;

architecture Behavioral of encoder is

begin
PROCESS(ENABLE,D_IN)
BEGIN
IF( ENABLE = '1') THEN
D_OUT <= "000";
ELSE
CASE D_IN IS
WHEN "00000001" => D_OUT <= "000";
WHEN "00000010" => D_OUT <= "001";
WHEN "00000100" => D_OUT <= "010";
WHEN "00001000" => D_OUT <= "011";
WHEN "00010000" => D_OUT <= "100";
WHEN "00100000" => D_OUT <= "101";
WHEN "01000000" => D_OUT <= "110";
WHEN "10000000" => D_OUT <= "111";
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS;


end Behavioral;











4. Program for 8:3 encoder (with Priority)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity encoder2 is
Port ( Enable : in STD_LOGIC;
D_in : in STD_LOGIC_VECTOR (7 downto 0);
D_out : out STD_LOGIC_VECTOR (2 downto 0));
end encoder2;

architecture Behavioral of encoder2 is
begin
PROCESS(ENABLE,D_IN)
BEGIN
IF ( ENABLE = '1') THEN
D_OUT <= "000";
ELSE
CASE D_IN IS
WHEN "00000001" => D_OUT <= "000";
WHEN "00000010" => D_OUT <= "001";
WHEN "00000100" => D_OUT <= "010";
WHEN "00001000" => D_OUT <= "011";
WHEN "00010000" => D_OUT <= "100";
WHEN "00100000" => D_OUT <= "101";
WHEN "01000000" => D_OUT <= "110";
WHEN "10000000" => D_OUT <= "111";
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS;
end Behavioral;








Result:






5. PRORAM FOR 8:1 MUX

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity Multiplexer is
Port ( Sel : in STD_LOGIC_VECTOR (2 downto 0);
A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
D : in STD_LOGIC;
E : in STD_LOGIC;
F : in STD_LOGIC;
G : in STD_LOGIC;
H : in STD_LOGIC;
D_OUT : out STD_LOGIC);
end Multiplexer;

architecture Behavioral of Multiplexer is

begin

PROCESS (SEL,A,B,C,D,E,F,G,H)
BEGIN
CASE SEL IS
WHEN "000" => D_OUT <= A;
WHEN "001" => D_OUT <= B;
WHEN "010" => D_OUT <= C;
WHEN "011" => D_OUT <= D;
WHEN "100" => D_OUT <= E;
WHEN "101" => D_OUT <= F;
WHEN "110" => D_OUT <= G;
WHEN "111" => D_OUT <= H;
WHEN OTHERS => NULL;
END CASE;
END PROCESS;

end Behavioral;

Result:









6. PROGRAM TO CONVERT 4 BIT BINARY NO TO GRAY CODE.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity converter is
Port ( B : in STD_LOGIC_VECTOR (3 downto 0);
G : out STD_LOGIC_VECTOR (3 downto 0));
end converter;

architecture Behavioral of converter is

begin
G(3)<= B(3);
G(2)<= B(3) XOR B(2);
G(1)<= B(2) XOR B(1);
G(0)<= B(1) XOR B(0);


end Behavioral;





















7. PROGRAM TO CONVERT 4 BIT GRAY CODE TO BINARY

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity converter is
Port ( G : in STD_LOGIC_VECTOR (3 downto 0);
B : inout STD_LOGIC_VECTOR (3 downto 0));
end converter;

architecture Behavioral of converter is

begin
B(3)<= G(3);
B(2)<= B(3) XOR G(2);
B(1)<= B(2) XOR G(1);
B(0)<= B(1) XOR G(0);


end Behavioral;



















8. N-BIT COMPARATOR

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Comparator is
GENERIC (N: INTEGER := 3);
Port (A,B: IN STD_LOGIC_VECTOR(N DOWNTO 0);
ALB : out STD_LOGIC;
AEB : out STD_LOGIC;
AGB : out STD_LOGIC);
end Comparator;

architecture Behavioral of Comparator is

begin
PROCESS(A,B)
BEGIN
ALB<='0'; AGB<='0'; AEB<='0';
IF A=B THEN
AEB<='1';
ELSIF A>B THEN
AGB<='1';
ELSE
ALB<='1';
END IF;
END PROCESS;


end Behavioral;





RESULT:










9. PROGRAM FOR HALF ADDER

ibrary IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity HALFADDER is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
S : out STD_LOGIC;
C : out STD_LOGIC);
end HALFADDER;

architecture Behavioral of HALFADDER is

begin
S <= A XOR B;
C<= A AND B;

end Behavioral;















RESULT:










10. PROGRAM FOR FULL ADDER

Library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity HALFADDER is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
CIN:in std_logic;
S : out STD_LOGIC;
COUT : out STD_LOGIC);
end HALFADDER;

architecture Behavioral of HALFADDER is

begin
PROCESS(A,B,CIN)
BEGIN
S<= A XOR B XOR CIN;
COUT<= (A AND B) OR (B AND CIN) OR (CIN AND A);
END PROCESS;


end Behavioral;










RESULT:










11. SR FLIP FLOP

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity SRFF is
Port ( S : in STD_LOGIC;
R : in STD_LOGIC;
CLK : in STD_LOGIC;
Q: BUFFER STD_LOGIC);
end SRFF;

architecture Behavioral of SRFF is

begin
PROCESS(CLK)
BEGIN
IF CLK='1' AND CLK'EVENT THEN
IF(S='0' AND R='0')THEN Q<=Q;
ELSIF(S='0' AND R='1')THEN Q<='0';
ELSIF(S='1' AND R='0')THEN Q<='1';
ELSIF (S='1' AND R='1')THEN Q<='Z';
END IF;
END IF;
END PROCESS;


end Behavioral;






RESULT:




















12. D FLIP FLOP

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity dff is
Port ( D : in STD_LOGIC;
CLK : in STD_LOGIC;
Q : out STD_LOGIC);
end dff;

architecture Behavioral of dff is

begin
PROCESS(CLK)
BEGIN
IF(CLK'EVENT AND CLK='1')THEN
Q<=D;
END IF;
END PROCESS;

end Behavioral;












RESULT:










13. T FLIP FLOP

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity TFF is
Port ( CLK,T : in STD_LOGIC;
RST : in STD_LOGIC;
Q : out STD_LOGIC;
QB : out STD_LOGIC);
end TFF;

architecture Behavioral of TFF is
SIGNAL TEMP:STD_LOGIC;
begin
PROCESS(CLK,RST)
BEGIN
IF(RST='1')THEN
TEMP<='0';
ELSIF(CLK='1' AND CLK'EVENT)THEN
IF(T='1')THEN
TEMP<=NOT TEMP;
END IF;
END IF;
END PROCESS;
Q<=TEMP;
QB<=NOT TEMP;

end Behavioral;





RESULT:










14. JK FILPFLOP

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity JKFF is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
J : in STD_LOGIC;
K : in STD_LOGIC;
Q : out STD_LOGIC;
QB : out STD_LOGIC);
end JKFF;

architecture Behavioral of JKFF is
SIGNAL TEMP :STD_LOGIC;
begin
PROCESS(CLK,RST)
VARIABLE JK:STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
IF(RST='1')THEN
TEMP<='0';
ELSIF(CLK='1' AND CLK'EVENT)THEN
JK:=J & K;
CASE JK IS
WHEN "01"=>TEMP<='0';
WHEN "10"=>TEMP<='1';
WHEN "11"=>TEMP<=NOT TEMP;
WHEN OTHERS=>TEMP<=TEMP;
END CASE;
END IF;
END PROCESS;
Q<=TEMP;
QB<=NOT TEMP;
end Behavioral;












14. 4-BIT BINARY UP COUNTER

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity BINARYUPCOUNTER is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
BINCOUNT : out STD_LOGIC_VECTOR (3 downto 0));
end BINARYUPCOUNTER;

architecture Behavioral of BINARYUPCOUNTER is
SIGNAL BINCOUNT1:STD_LOGIC_VECTOR(3 DOWNTO 0);
begin
PROCESS(CLK,RST)
BEGIN
IF(RST='1')THEN
BINCOUNT1<=(OTHERS=>'0');
ELSIF(CLK='1' AND CLK'EVENT)THEN
IF(BINCOUNT1="1111")THEN
BINCOUNT1<="0000";
ELSE
BINCOUNT1<=BINCOUNT1+1;
END IF;
END IF;
END PROCESS;
BINCOUNT<=BINCOUNT1;


end Behavioral;










RESULT:









15 .4-BIT BINARY DOWN COUNTER

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity BINARYDOWNCOUNTER is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
BINCOUNT : out STD_LOGIC_VECTOR (3 downto 0));
end BINARYDOWNCOUNTER;

architecture Behavioral of BINARYDOWNCOUNTER is
SIGNAL BINCOUNT1:STD_LOGIC_VECTOR(3 DOWNTO 0);
begin
PROCESS(CLK,RST)
BEGIN
IF(RST='1')THEN
BINCOUNT1<=(OTHERS=>'0');
ELSIF(CLK='1' AND CLK'EVENT)THEN
IF(BINCOUNT1="0000")THEN
BINCOUNT1<="1111";
ELSE
BINCOUNT1<=BINCOUNT1-1;
END IF;
END IF;
END PROCESS;
BINCOUNT<=BINCOUNT1;

end Behavioral;





RESULT:





16. BCD down counter

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity BCDUPCOUNTER is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
BCDCOUNT : out STD_LOGIC_VECTOR (3 downto 0));
end BCDUPCOUNTER;

architecture Behavioral of BCDUPCOUNTER is
SIGNAL BCDCOUNT1:STD_LOGIC_VECTOR(3 DOWNTO 0);
begin
PROCESS(CLK,RST)
BEGIN
IF(RST='1')THEN
BCDCOUNT1<=(OTHERS=>'0');
ELSIF(CLK='1' AND CLK'EVENT)THEN
IF(BCDCOUNT1="0000")THEN
BCDCOUNT1<="1111";
ELSE
BCDCOUNT1<=BCDCOUNT1-1;
END IF;
END IF;
END PROCESS;
BCDCOUNT<=BCDCOUNT1;


end Behavioral;





Result:

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